Delay Error with Meta - Stability Detection and Correction Using CMOS Transmission Logic
نویسندگان
چکیده
منابع مشابه
Delay Error with Meta-stability Detection and Correction Using Cmos Transmission Logic
The new technologies are giving the advance systems which are capable to perform multiple operations simultaneously. This all is possible by the scaling technology where the overall chip size get reduced but due to manufacturing and fabrication defects, certain design uncertainty arises thereby affecting the transistor performance by timing related effect. The robust circuit where sufficient ma...
متن کاملUsing codes for error correction and detection
Absiruct-A linear code C over GF( q) is good for t-error-correction and error detection if P(C, t; c) I P(C, t; (q 1)/q) for all z, 0 s c I (q 1)/q, where P( C, t; c) is the probability of an undetected error after a codeword in C is transmitted over a q-ary symmetric channel with error probability c and correction is performed for ail error patterns with t or fewer errors. A sufficient conditi...
متن کاملTransducers and the Properties of Error-Detection, Error-Correction, and Finite-Delay Decodability
When the words of a language are communicated via a noisy channel, the language property of error-detection ensures that no word of the language can be transformed to another word of the language. On the other hand, the property of error-correction ensures that the channel cannot transform two different words of the language to the same word. In this work we use transducers to model noisy chann...
متن کاملLogic Bug Detection and Localization Using Symbolic Quick Error Detection
We present Symbolic Quick Error Detection (Symbolic QED), a structured approach for logic bug detection and localization which can be used both during pre-silicon design verification as well as post-silicon validation and debug. This new methodology leverages prior work on Quick Error Detection (QED) which has been demonstrated to drastically reduce the latency, in terms of the number of clock ...
متن کاملLogic design error diagnosis and correction
| Logic veriication tools are often used to verify a gate-level implementation of a digital system in terms of its functional speciication. If the implementation is found not to be functionally equivalent to the speciication, it is important to correct the implementation automatically. This paper describes a formal method for the diagnosis and correction of logic design errors in an incorrect g...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: International Journal of VLSI Design & Communication Systems
سال: 2012
ISSN: 0976-1527
DOI: 10.5121/vlsic.2012.3403